1. Technical Field of the Invention
This invention relates generally to integrated circuits and more particularly to a programmable application specific integrated circuit.
2. Description of Related Art
As is known, integrated circuits are used in a wide variety of electronic devices, such as computers, telecommunication equipment (servers, switches, private branch exchanges, routers, bridges, et cetera), cellular telephones, land lined telephones, home entertainment equipment, et cetera. Such integrated circuits can contain millions of transistors to perform a variety of fixed or programmable functions. The functions may be proprietary and/or in accordance with one or more standards. Typically, the more programmability an integrated circuit provides, the more gates (i.e., transistors) it requires to implement. Not surprisingly, the cost of design and manufacture of integrated circuits increase as the number of gates increase. Also, the yield (i.e., the number of usable integrated circuits per total number of integrated circuits fabricated on a wafer) decreases as the size of the integrated circuit die increases, which is dependent on the particular integrated circuit fabrication process used.
As such, integrated circuit designers and system designers (i.e., engineers who design electronic equipment that includes integrated circuits) are faced with design trade-off decisions. Those being, design and/or use applications specific integrated circuits (ASIC), which are smaller and thus less expensive but are not programmable, or used programmable integrated circuits such as field programmable gate arrays, microprocessors, microcontrollers, which provide programmable functions, but at an increased cost and size. Alternatively, the designers may use a combination of ASICs with programmable integrated circuits.
For many standard based user devices (e.g., cellular telephones, wireless local area network modems, computers, et cetera), ASICs are the preferred integrated circuit because of cost, operating speed, and ease of use. Such ASICs may contain analog circuitry, digital circuitry and/or memory to perform the prescribed function or functions of the particular standard. Typically, the digital circuits include digital logic blocks to perform specific logic functions and data flow control state machines that control the flow of data through the digital logic blocks.
FIG. 1 is a schematic block diagram of digital circuits of an application specific integrated circuit (ASIC). As shown, the digital circuitry receives digital input data and produces digital output data therefrom in accordance with a particular logic function of the digital circuitry. In addition, the flow of data through the digital circuitry is controlled based on data flow control signals produced by the state machine. The state machine includes state machine logic that generates the data flow control signals based on fixed codes. For example, the fixed codes may indicate the number of clock cycles for the data to be processed by a particular section of the digital circuitry, branches within the digital circuitry based on conditions, et cetera.
Typically, an integrated circuit (IC) designer may utilize an integrated circuit design tool such as Verilog or VHDL (hardware description language) to fabricate the state machine and corresponding digital circuitry. Utilizing one of these IC design tools, the state machine is typically generated utilizing case statements to produce the corresponding data flow control signals. Alternatively, the IC designer may fabricate the state machine as a timing sequencer that utilizes micro-code instructions to produce the data flow control signals.
While the digital circuitry and state machine of FIG. 1 provide a specific desired function or functions, it is not programmable. As such, if an error was made in the generation of the fixed code, the specification changes, and/or other errors exist in the design of the digital circuitry and/or state machine, the ASIC needs to be at least partially re-designed to overcome the error and/or specification change. Accordingly, a new mask set, or portion thereof, must be fabricated and a new version of the ASIC manufactured before testing can resume. As is known, the generation of a new mask set and subsequent fabrication of a revised ASIC takes many weeks to obtain silicon for testing, which substantially extends the development cycle of the ASIC.
FIG. 2 is a schematic block diagram of an alternate state machine coupled to digital circuitry. The state machine generates the data flow control signals, which control the flow of data through the digital circuitry. In this embodiment, however, the state machine includes an instruction register, state machine logic, an address generator, which addresses memory, which may be on-chip and/or off-chip. The memory stores the corresponding instructions for the state machine logic. While this implementation allows for re-programmability of the state machine, the ASIC must include an address bus, which may be 16 bits, 32 bits or 64 bits, depending on the size of the memory, and a data bus, which may be 16 bits, 32 bits or 64 bits depending on the size of the memory, and a fully functional address generator. As such, in comparison with the state machine of FIG. 1, the state machine of FIG. 2 requires a significant amount of extra gates to implement. Also, the state machine of FIG. 2 is significantly larger in die area than the state machine of FIG. 1.
In addition to the above, an ASIC may have many state machines (e.g., ten or more), and each of these state machines may only have a small number of states (e.g., ten states or less), where each state corresponds to a timing sequencer micro-code instruction. Typically, an ASIC includes many small memory blocks (e.g., random access memory) to store the micro-instructions of each of the numerous state machines. In current IC manufacturing processes (e.g., CMOS), the memory block memory blocks must be of a minimum size, which for RAM is approximately 128 words. As such, the memory blocks are significantly greater than the 10 micro-code instructions per state machine need, which is not economical. Further, many small memory blocks may cause problem in layout of integrated circuit that mixes standard library cells with custom cells.
While ASICs and other types of integrated circuits provide a great deal of functionality in a very small package, testing the millions of transistors in the integrated circuits is an ever-increasing challenge. Currently, many ASICs include test circuitry such as scan insertion, memory built-in self test (BIST) insertion, logic BIST insertion and/or boundary scan insertion. In general, boundary scan insertion tests for connections between the ASIC and the printed circuit board on which it is mounted. The memory BIST includes a logic controller that utilizes various algorithms to generate input patterns to exercise the memory of the ASIC. The logic BIST is similar to the memory BIST, but it exercises the logic of the ASIC via one or more scan chains (scan chains will be described subsequently with reference to FIG. 4) as opposed to memory.
Scan insertion involves replacing the flip-flops of the digital logic circuits of the ASIC with scan enabled flip-flops for the sole purpose of testing. FIG. 3 illustrates a schematic block diagram of a scan enabled flip-flop. As shown, the scan enabled flip-flop includes a multiplexor and a flip-flop. During scan mode, the multiplexor is enabled to pass the scan input data (SD) to the flip-flop. In addition, the clocking of the flip-flop may be controlled via the memory BIST or logic BIST. Once testing is over, the scan enable signal (SE) to the multiplexor is set in normal mode such that normal data (D) is provided to the flip-flop via the multiplexor.
FIG. 4 is a schematic block diagram of a portion of an ASIC that includes a plurality of scan enabled flip-flops coupled together via a scan chain and digital logic. The digital logic may be the state machine logic of FIG. 1 or 2 and/or the digital circuitry of FIGS. 1 and 2. As shown, the plurality of scan enabled flip-flops are coupled in a serial fashion to produce the scan chain, which is illustrated via the bold lines. Accordingly, a first scan enabled flip-flop of the scan chain receives scanned input data (SD in). The remainder of the flip-flops in the scan chain receive their scanned input (SD) from the output of the preceding flip-flop. Accordingly, during scan mode, the test circuitry may insert a series of patterns via the scan chain to test a majority of the ASIC.
While there is a variety of design choices for IC designers and systems designers, a need still exists for a programmable application specific integrated circuit (ASIC) design that does not substantially increase gate count with respect to fixed logic ASICs, but provides a great deal of programmability, thus avoiding the need to generate new mask sets when errors are discovered in the design and/or the specifications change during the development phase.